1. Field of the Invention
This invention relates to a liquid crystal display device, especially a liquid crystal display device with an outer connection region that connects a pixel region and an outer circuit and its manufacturing method.
2. Description of the Related Art
Demands for liquid crystal display device have dramatically increased in recent years as portable electronics such as cell phone and digital camera are getting popular. COG, or Chip on Glass, is known as a liquid crystal display devices, where an outer circuit is mounted on a glass substrate, one of the configuring parts of the liquid crystal display device. The liquid crystal display device of prior art with an outer circuit mounted through COG method is explained by referring to FIGS. 10 and 11. FIG. 10 is a plan view showing the configuration of the liquid crystal display device.
A pixel region 100P configured from a plurality of display pixels with pixel selection thin film transistors (TFT) is formed on a liquid crystal display device, a panel 100 made of a glass substrate, as shown in FIG. 10.
In the pixel region 100P, an N channel type pixel election TFT 103, for example, is disposed near the crossing point between a scanning line 101 extending in row direction and a data line 102 extending in column direction. The gate of the pixel selection TFT 103 is connected to the scanning line 101 and the source of the pixel selection TFT 103 is connected to the data line 102. A pixel selection signal G outputted from a vertical driving circuit 201 is applied to the scanning line 101, controlling on and off of the pixel selection TFT 103. A display signal D from a horizontal driving circuit 202 is applied to the data line 102.
A pixel electrode and a common electrode, both of which are not shown in the figure, are formed on an opposite side of the liquid crystal layer LC. The drain of the pixel selection TFT 103 is connected to the pixel electrode. The liquid crystal layer LC is shown as a capacitor as it functions as a dielectric body. A storage capacitance, not shown in the figure, is also connected to the drain of the pixel election TFT 103 for holding the display signal D applied to the pixel electrode for one horizontal period. Although the data line 102 is connected to the source and the pixel electrode is connected to the drain of the pixel selection TFT 103 in the figure, it is possible to connect the pixel electrode to the source and the data line 102 to the drain.
An outer connection region 107 that connects the vertical driving circuit 201 and the horizontal driving circuit 202 to an outer circuit (such as the driving circuit supplying signals including a standard clock and electric source) is formed outside of the pixel region 100P, that is, the peripheral area of the liquid crystal display panel 100. A wiring layer, where wire comes out from the vertical driving circuit 201 and the horizontal driving circuit 202, and a terminal 108 are disposed in the outer connection region 107. A metal bump 150, which is a terminal of the outer circuit, not shown in the figure, is connected to the terminal 108 of the outer connection region 107 through a plurality of same-sized conductive resin balls 140 and an anisotropic conductive film (ACF) 141 made of insulating adhesive agent.
FIG. 11 is a cross-sectional view of the terminal 108 of the outer connection region 107 along with the line X-X in FIG. 10. A gate metal layer 111 that is made of the same material as that of the gate electrode of the pixel election TFT 103 is formed on a substrate 110 in the outer connection region 107, as shown in FIG. 11. A gate insulating film 112 and a flattening film 113 are formed with an opening 120 for exposing a part of the gate metal layer 111 on the substrate 110.
A layer (referred to as an ITO layer 114, hereinafter) made of the same material as that of the gate electrode, such as ITO (indium tin oxide), not shown in the figure, is formed on the part of the gate metal layer 111 exposed from the opening 120. The anisotropic conductive film 141 that includes a plurality of conductive resin balls 140 is formed on the ITO layer including the inside of the opening 120. The metal bump 150, which is the terminal of the outer circuit, is placed on the ITO layer 114, the top layer electrode of the terminal 108 of the outer connection region 107. Then, they are connected through the thermal pressuring.
Next, the operation of the liquid crystal display device will be explained. The pixel selection TFT 103 turns on when a high level pixel selection signal G from the outer circuit, not shown in the figure, and the vertical driving circuit 201 is applied to the scanning line 101 for one horizontal period. Then, the display signal D outputted from the outer circuit not shown in the figure or the horizontal driving circuit 202 to the data line 102 is stored in the storage capacitance, not shown in the figure, through the pixel selection TFT 103 and applied to the pixel electrode mentioned above. Then, the electric field of the liquid crystal layer LC is controlled for one horizontal period according to the display signal D, and the alignment of the liquid crystal molecule is controlled according to the electric field. A black display or a white display of the liquid crystal is achieved. A desirable image can be obtained by performing this operation through the entire display region for one field period.
The technical reference related to this invention is found in Japanese Patent Application Publication No. 2002-229058.
However, the distance between the surface of the metal bump 150 that is the terminal of the outer circuit not shown in the figure and the surface of the ITO layer 114 is greater inside the opening 120 than outside the opening 120 of the outer connection region 107, as shown in the figure. Therefore, a conductive resin ball 140 in the anisotropic conductive film stays untouched either by the metal bump 150 of the outer circuit or the ITO layer 114. That leads to the poor electric connection between the metal bump 150 and the terminal 108 of the outer connection region 107. As a result, the yield rate of the liquid crystal display device with the outer circuit connected is deteriorated.